According to spread of digital equipments and development of digital contents such as Internet, importance of a storage device which stores digital data therein increasingly becomes high.
Various performances are required for the storage device, but important performances among them are that a capacity of recording data is large, that a data transmission rate showing a time required to read/write a fixed amount of data is high, that power required to record a fixed amount of data is low, and the like.
A device to which attention is paid as a digital storage device in recent years is a solid state device (hereinafter, called “SSD”) using a semiconductor memory, centered on a flash memory. Since page data recording to/reading from the SSD is possible, the SSD includes such a matter that the data transmission rate is high as one of merits thereof, and a SSD for personal utilization in a personal computer or the like is frequently used because of this merit.
Furthermore, the SSD is expected as a storage device for business use requiring a high data transmission rate. However, since cost per bit (hereinafter simply referred to as “bit cost”) is currently high, application of the SSD to a storage system for business use is not very popular. One of the reasons is that the semiconductor device is manufactured via many steps. And it is necessary to make a cell area per bit small to achieve a large capacity in the SSD, and micromachining technique is required to do this.
Therefore, in order to reduce the bit cost of the SSD, it is required to increase a recording capacity per chip while suppressing increase of manufacturing cost per chip.
One example is a 3D technology of a semiconductor device described in Japanese Patent Application Laid-open Publication 2008-160004 (Patent Document 1). In an ordinary 3D technology, devices each composed of one layer are manufactured along an X-Y direction of a semiconductor substrate in a two-dimensional manner, and they are stacked so as to have a three-dimensional structure by any method. In this method, however, though cell area per bit can be reduced, manufacturing cost per bit cannot be reduced.
On the other hand, in the method described in Patent Document 1, recording regions holding data and Si (silicon) channels introducing current into the recording regions are continuously formed along a vertical direction (Z direction) of a semiconductor substrate. Furthermore, a plurality of gate electrodes of MOS transistors for selecting one of the recording regions in the vertical direction is formed in a vertical direction. Furthermore, these structures are arranged along the X-Y direction of the semiconductor device in a two-dimensional manner. Selection from a plurality of structures arranged in the X-Y direction is performed by a bit line and a word in the same manner as the DRAM or the like. According to such a structure, the recording region is selected three-dimensionally so that a three-dimensional recording device is realized.
According to the 3D technology in the above-mentioned Patent Document 1, since the structure along the vertical direction (Z direction) of the semiconductor device can be manufactured by a collective process, and size reduction in the X-Y direction becomes unnecessary due to recording many bits in the vertical direction, it is possible to increase the recording capacity per chip while suppressing increase of manufacturing cost per chip.
In recent years, as one of alternative technologies of the above-mentioned flash memory, a phase change memory device has been proposed. This phase change memory device is obtained by applying, to a semiconductor memory, a principle of DVD-RAM, DVD-RW, and the like which is a rewritable optical disk which have been put in the market, and digital data is recorded by reversibly changing a state of a recording film, which is made of a phase change material such as chalcogenide, between an amorphous phase and a crystal phase.
In the case of the phase change memory device, Joule heat generated by causing current to flowing into the recording film is utilized for reversible change between the amorphous phase and the crystal phase. That is, when the recording film is changed from the crystal phase to the amorphous phase, the recording film is locally melted by causing high current to flow in the recording film. At this time, when a cooling rate of the melted region after stop of current supply is sufficiently fast, since kinetic energy of atoms before atoms form arrangement of minimal energy becomes small, an amorphous phase is formed in a local area within the recording film. On one hand, when the recording film is changed from the amorphous phase to the crystal phase, current smaller than the above is caused to flow in the recording film to heat the recording film up to a temperature at which the recording film is crystallized. Furthermore, when data is read out, a difference in electric resistivity between the amorphous phase and the crystal phase is detected. Incidentally, the details of the technology about the phase change memory device have been summarized, for example, in Patent Document 1.
An example where the 3D technology described in the above-mentioned Patent Document 1 has been applied to the phase change memory device is described in Japanese Patent Application Laid-open Publication 2010-165982 (Patent Document 2). The phase change memory device has a structure where a recording film made of phase change material and a Si channel layer is in contact with each other, and it is configured such that an inversion layer is locally formed in the Si channel layer by applying a voltage to the gate electrode of a MOS transistor so that current is caused to flow in the recording film locally.
The structure of the above-mentioned phase change memory device is shown in FIG. 2. The periphery of a select bit (recording bit) which performs recording is composed of a word line (upper electrode) 20, a bit line (lower electrode) 21, a central portion dielectric film 22, a phase change recording film 23, an interface layer 24, a Si channel layer 25, and a gate insulation film 26, and gate electrodes 27 of a MOS transistor for selection. The word line 20 and the bit line 21 are each made of a metal film such as, for example, W (tungsten), and the gate electrodes 27 are each made of, for example, a Si (silicon) film. Furthermore, the phase change recording film 23 is made of, for example, a Ge2Sb2Te5 film, and the central portion dielectric film 22 and the gate insulation film 26 are each made of, for example, a SiO2 (oxide silicon) film.
In the device shown in FIG. 2, the phase change recording film 23 is continuously formed in a vertical direction, but since the recording bit is determined in accordance with a voltage applied to the gate electrode 27, phase change takes place within an area which is indicated by a broken line in the phase change recording film 23 (which is in the vicinity of the respective gate electrodes 27). That is, the portions indicated by the broken line serve as recording bits.
Here, for example, when a voltage is applied to the gate electrode 27a of the MOS transistor so that the resistance of an area which is indicated by the broken line in the Si channel layer 25 becomes larger than that of the interface layer 24 and the phase change recording film 23, current passes through a path indicated by an arrow. In this way, since current can be introduced into a local portion of the phase change recording film 23 so as to form an inversion layer, it is possible to select a bit to be recorded and read.
Furthermore, in the device shown in FIG. 2, an interface layer 24 is provided between the phase change recording film 23 and the Si channel layer 25. From this, it is possible to suppress mutual diffusion between elements constituting the phase change recording film 23 and elements constituting the Si channel layer 25, and to hold the temperature of the phase change recording film 23 constant at the time of recording data.
That is, since the Si channel layer 25 is higher in thermal conductivity than the central portion dielectric film 22, the temperature in the phase change recording film. 23 becomes low on the side closer the Si channel layer 25 than the central portion dielectric film 22, so that enormous power is required in order to raise the temperature of the phase change recording film 23 on the side of the Si channel layer 25 to a high temperature. Therefore, in order to solve this problem, the interface layer 24 for suppressing excessive thermal diffusion from the phase change recording film 23 to the Si channel layer 25 is provided.